Packet processing switch and methods of operation thereof

ABSTRACT

A packet processing integrated circuit chip includes a plurality of input ports configured to receive packets from respective external sources and a plurality of output ports configured to transmit packets to respective external recipients. The chip further includes a packet processor configured to process the received packets to generate new packets with new payloads according to selected ones of a plurality of packet processing scenarios based on destination addresses in the received packets. The plurality of packet processing scenarios may include individual packet processing scenarios and group packet processing scenarios that invoke parallel processing of a packet by selected ones of the individual packet processing scenarios. The chip may further include a packet switching fabric configured to route selected packets from the input ports to selected ones of the output ports without payload modification.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims the benefit of U.S. ProvisionalApplication Ser. No. 60/672,349, filed Apr. 18, 2005, the disclosure ofwhich is hereby incorporated by reference herein in its entirety.

BACKGROUND OF THE INVENTION

This invention relates to packet communications devices and methods and,more particularly, to packet switching devices and methods.

Increasing demand for communications services have generally increasedbandwidth requirements for network components. For example, theincreased volume of wireless communications has been generallyaccompanied by an increase in the bandwidth requirements betweenwireless terminals and base stations. Users demanding more informationand more services from their cell phones and other wireless devices canoverwhelm available bandwidth. Wireless service providers are migratingto 2.5G and 3G technologies to mitigate this problem. These technologiesgenerally enable more data per broadcast band than 2G technologies,which can be used to give more bandwidth to individual users or to servemore users in the same cell area.

An important aspect of 3G wireless communications systems is closed looppower control. For example, in wideband code division multiple access(WCDMA) systems, it is typically desirable that a base station becapable of telling a mobile terminal to adjust its transmission powerwithin 5 milliseconds after receiving a packet from the terminal. Thiscan be the most constraining limitation on total delay in the basestation, as it includes the round-trip delay of received radio signalsample going from an RF card, to a baseband card, and on to a controlcard, and back to the baseband card, RF card, and antenna. Each basestation may have several RF and baseband cards, and signal samples maybe transferred between any given RF card and any given baseband card.Reducing latency in transferring data between these cards tends to beimportant.

Different architectures may be used to convey data between such cards.In a full-mesh architecture, each RF card is connected to each basebandcard. A switched architecture provides a multiple-input multiple-outputswitch between the RF and baseband cards. The switched architecture canprovide improved scalability and flexibility, but may add more latencythan the full-mesh solution. Also, for smaller systems, a full-mesharchitecture may be less expensive than a switched architecture.

Integrated circuits (ICs) have been developed that can supportcommunications between base station components, such as RF cards andbaseband cards. For example, Spectrum Signal Processing Inc. offers theASIC-based Solano™ chip that can be used to interface processors, suchas digital signal processors (DSPs), RISC processors, and FPGAs, andsources of data, such as RF cards. The chip includes eight high-speedFIFOs, with associated control logic, that are paired to form fourfull-duplex channels. Tundra Semiconductor Corporation offers SerialRapidIO® chips that include a switching fabric that can be used toprovide a switched architecture between RF and baseband cards.

SUMMARY OF THE INVENTION

According to some embodiments of the present invention, a packetprocessing integrated circuit chip includes a plurality of input portsconfigured to receive packets from respective external sources and aplurality of output ports configured to transmit packets to respectiveexternal recipients. The chip further includes a packet processorconfigured to process the received packets to generate new packets withnew payloads according to selected ones of a plurality of packetprocessing scenarios based on destination addresses in the receivedpackets. The plurality of packet processing scenarios may includeindividual packet processing scenarios and group packet processingscenarios that invoke parallel processing of a packet by selected onesof the individual packet processing scenarios. The chip may furtherinclude a packet switching fabric configured to route selected packetsfrom the input ports to selected ones of the output ports withoutpayload modification.

In further embodiments, the packet processor is configurable to extractdata from payloads of the received packets and to process the extracteddata to produce the new packets with payloads having formats compatiblewith data structures of the external recipients. For example, the packetprocessor may be configurable to perform bit extension, bit truncation,bit reordering and/or bit arithmetic operations on the received packets.

According to additional embodiments of the present invention, timing ofeach packet processing scenario is controlled responsive to receivedpacket accumulation for the packet processing scenario. The packetprocessor may be configured to initiate packet accumulation for a packetprocessing scenario responsive to an initialization signal.

In some embodiments of the present invention, an interface circuit forconveying data between a first plurality of circuit cards and a secondplurality of circuit cards includes a plurality of input portsconfigured to receive packets from respective ones of the firstplurality of circuit cards and a plurality of output ports configured totransmit packets to respective ones of the second plurality of circuitcards. The interface circuit further includes a packet processorconfigured to process the received packets to generate new packets withnew payloads according to selected ones of a plurality of packetprocessing scenarios based on destination addresses in the receivedpackets. The interface circuit may further include a packet switchingfabric configured to route selected packets from the input ports toselected ones of the output ports without payload modification. In somewireless communications embodiments, the plurality of input ports areconfigured to receive packets from respective ones of a plurality of RFcards and the plurality of output ports are configured to transmitpackets to respective ones of a plurality of baseband cards.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating a packet processing switchintegrated circuit chip according to some embodiments of the presentinvention.

FIG. 2 is a schematic diagram illustrating a packet processing switchintegrated circuit chip according to further embodiments of the presentinvention.

FIGS. 3 and 4 illustrate exemplary port configurations for a packetprocessing switch according to some embodiments of the presentinvention.

FIG. 5 illustrates an exemplary packet flow architecture for a packetprocessing switch according to some embodiments of the presentinvention.

FIGS. 6 and 7 illustrate using packet destination addresses to routepackets in a packet processing switch according to further embodimentsof the present invention.

FIG. 8 illustrates an exemplary packet processing scenario structureaccording to some embodiments of the present invention.

FIGS. 9 and 10 illustrate exemplary packet payload formats that may beused with some embodiments of the present invention.

FIG. 11 illustrates exemplary channel queues of a packet processoraccording to further embodiments of the present invention.

FIGS. 12 and 13 illustrate exemplary summing operations of a packetprocessor according to some embodiments of the present invention.

FIG. 14 illustrates an exemplary packet processing switch interfacecircuit application according to further embodiments of the presentinvention.

FIG. 15 illustrates exemplary packet structures for source cards of theapplication illustrated in FIG. 14.

FIG. 16 illustrates exemplary sample queues formed from the packetsillustrated in FIG. 15.

FIGS. 17-20 illustrate exemplary output packets produced from thepackets of FIG. 15 by various packet processing scenarios according tovarious embodiments of the present invention.

FIG. 21 illustrates exemplary operations of a packet processor accordingto some embodiments of the present invention.

FIGS. 22 and 23 illustrate exemplary packet processing initializationoperations according to further embodiments of the present invention.

FIGS. 24-27 illustrate exemplary timing relationships for packetprocessing scenarios according to some embodiments of the presentinvention.

FIGS. 28 and 29 illustrate packet processors and exemplary operationsthereof according to further embodiments of the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Specific exemplary embodiments of the invention now will be describedwith reference to the accompanying drawings. This invention may,however, be embodied in many different forms and should not be construedas limited to the embodiments set forth herein; rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the invention to thoseskilled in the art. In the drawings, like numbers refer to likeelements. It will be understood that when an element is referred to asbeing “connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. Furthermore, “connected” or “coupled” as used herein mayinclude wirelessly connected or coupled. As used herein the term“and/or” includes any and all combinations of one or more of theassociated listed items.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless expressly stated otherwise. Itwill be further understood that the terms “includes,” “comprises,”“including” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

FIG. 1 illustrates a packet-processing switch integrated circuit (IC)chip 100 according to some embodiments of the present invention. Thechip 100 includes input ports 110 that are configured to receive datapackets. Packets received at the input ports 110 are selectively routedto a packet processor 130 or a switching fabric 140. The switchingfabric 140 provides for routing of the received packets to output ports120 of the chip 100 without payload modification.

The packet processor 130 synthesizes new packets with new payloads fromselected packets received at the input ports 110 according to selectedpacket processing scenarios (PPScs) 132, with the synthesized packetsbeing transmitted to external recipient devices via the output ports120. As explained in detail below, the packet processing scenarios 132may include various payload manipulations, such as bit extension, bittruncation, bit reordering (e.g., interleaving and/or flipping), andcombining (e.g., summing or other arithmetic operations) of payloadsfrom multiple received packets. Thus, for example, when used in a signalsample processing application such as in a wireless base station, thechip 100 can relieve the external recipient, e.g., a digital signalprocessor (DSP) or chip rate processor (CRP), of the burden ofreformatting a received signal sample stream for downstream operations,such as baseband processing. In addition, the packet processingscenarios 132 may be user-configurable, allowing the chip to be used fora variety of different communications protocols and/or messagingformats.

In various embodiments of the present described herein, a packetprocessing chip, such as the chip 100 illustrated in FIG. 1, may beconfigured to provide packet communications compliant with the RapidIO™interconnect architecture, which includes physical and logicalcommunications specifications for inter-device communications, asgenerally described at www.rapidio.org. It will be appreciated however,that although the exemplary embodiments described herein relate toRapidIO™-compliant packet processing switch chips and operationsthereof, the present invention may use other packet communicationarchitectures.

As shown in FIG. 2, a packet processing switch IC chip 200 according tofurther embodiments of the present invention may be user-configurable toprovide various port configurations, packet processing scenarios, and/orswitching functions defined in, for example, configuration registers250. The configuration registers 250 may, for example, store parametersfor packet processing scenarios 232 implemented by a packet processor230, parameters for operations of a switching fabric 240 and/orparameters for configuration of input and output ports 210, 220. Asshown, the configuration registers 250 may be configured via one of theinput ports 210 and/or via an inter-integrated circuit (I²C) businterface 260.

An example of an input/output port configurability scheme is illustratedin FIG. 3. In the illustrated example, 40 input/output links (lanes) maybe programmable into 4x or 1x ports. Each link may, for example, beconfigured to handle long and short haul serial transmission as defined,for example, by the RapidIO™ serial specifications. Links 0-3 areprogrammable into one 4x or one 1x port, Links 4-7 are programmable intoone 4x or four 1x ports, and Links 20-23 can be programmed as one 4xport. In the illustrated example, each link is a part of four-link groupthat is configured together, i.e., Link 3 is not configured with Links4,5,6, and 7. The ports are numbered from Link 0 to Link 40 in orderedfashion. For example, if Links 0-3 are configured as a 4x port, they areassigned to be port 0; if links 4-7 are configured as individual 1xports, they are assigned to port numbers 1 to 4. Table 1 illustratessome exemplary configurations: TABLE 1 Number Total of 4x Max numberTotal Links ports = Configuration ports (A) of 1x ports (B) Used = 4A +B A + B 1 10  — 40 10 2 9  4 40 13 3 8  8 40 16 4 7 12 40 19 5 6 16 4022 6 5 16 36 21 7 4 20 36 24 8 3 20 32 23 9 2 20 28 22 10  1 23 24 2111  — 24 24 24

Referring again to FIG. 2, the configuration registers 250 may includeregisters to define port configuration, speed and/or timing (longrun/short run), and other port characteristics. These registers can beprogrammed, for example, through the I²C bus interface 260 during aninitialization procedure. In some embodiments, the I²C interface 260 maynot be employed, and packets received via the input ports 210 may beused instead for device configuration. In such implementations, theinput ports 210 may have a default (e.g., power-on) configuration toenable communication with the configuration source. This initialconfiguration does not have to be the end-desired configuration, but canallow communications to begin with the chip such that a desiredconfiguration can be programmed. An exemplary power-on configuration isshown in FIG. 4, where Link 0 is set to be a 1x port 0 operating at 1.25Gb/s, Links 4-7 are set to be 1x ports 1-4 operating at 1.25 Gb/s, andthe remaining links are assigned to 4x, 1.25 Gb/s ports.

FIG. 5 illustrates an exemplary packet flow architecture for a packetprocessing switch IC chip 500 according to further embodiments of thepresent invention. The chip 500 includes input ports 510 including inputFIFOs 512 that receive packets from an external source. The receivedpackets are transferred from the input FIFOs 512 to either a packetprocessor 530 or a switching fabric 540, for example, using destinationaddresses therein, as described in further detail below. The packetprocessor 530 and the switching fabric 540 respectively routesynthesized packets or payload-unmodified packets to output ports 520,shown as including output FIFOs 524 and associated muxes 522.

Assuming, for purposes of the illustrated embodiments, that the receivedpackets are RapidIO™ packets that include priority fields therein, thereceived packets intended for the switching fabric 540 may be stored ininput buffers 542 based on the priority information in the receivedpackets, and provided to a packet switch 544 according to the prioritystructure of the input buffers 542. Respective groups of the inputbuffers 542 are associated with respective ones of the input ports 510.The priority structure of each group of input buffers 542 may beuser-configurable. For example, certain buffers may be assigned (e.g.,using configuration registers) to receive packets having different onesof RapidIO™ priority levels 0-3. The switch 544 routes the packets fromthe input buffers 542 to various ones of a plurality ofpriority-structured groups of output buffers 546, with respective onesof the groups of output buffers 546 being associated with respectiveones of the output ports 520.

In the packet processor 530, received packets to be processed in packetprocessing scenarios 534 are stored in input buffers 532. The packetprocessing scenarios 534 synthesize packets from the stored receivedpackets. The synthesized packets are stored in output buffers 536,respective groups of which are associated with respective ones of theoutput ports 520. The synthesized packets may include priorityinformation recovered from the received packets. The packets stored inthe output buffers 536, 546 may be routed to the output ports 520 using,for example, round robin scheduling algorithms.

According to certain embodiments of the present invention illustrated inFIG. 6, routing of a received packet 600 to a packet processor 610 or aswitching fabric 620 may be controlled based on a destination address601 included in the received packet. In particular, respectivedestination addresses may be reserved for respective packet processingscenarios 612 supported by the packet processor 610, while otheraddresses are mapped to the switching fabric 620. Such an approach maybe advantageous because it may be desirable that manipulation by thepacket processor 610 be transparent to the sending and/or receivingdevice.

As shown in FIG. 7, packet processing scenarios implemented by a packetprocessor may include individual packet processing scenarios 710 andgroup packet processing scenarios 720. The individual packet processingscenarios 710 may be assigned to certain destination addresses 701 ofinput packets 700. The individual packet processing scenarios may beuser configurable using, for example, configuration registers (e.g., theregisters 250 of FIG. 2). Such configuration registers may, for example,define payload formats and operations performed on packet payloads forthe particular packet processing scenarios. The group packet processingscenario addresses 720 may have other destination addresses 710 assignedthereto. As illustrated, the group packet processing scenarios 720 maybe used to cause received packets to be multicast to groups of theindividual packet processing scenarios 710 for parallel processing. Suchgroupings of individual packet processing scenarios may be configurableusing, for example, configuration registers.

FIG. 8 illustrates an exemplary packet processing scenario 800 accordingto some embodiments of the present invention. The scenario 800 includessample processing block 810, which may include, depending on theconfiguration of the scenario 800, initial sample and sub-sample leveloperations, such as increasing (padding) or decreasing the number ofbits in a sample and/or flipping the order of bits and/or subsamplesbefore queuing samples associated with separate channels (e.g.,antennas) in separate queues in a queuing block 820. The queued samplesmay be further processed in the sample processing block 810 beforetransmission to a packet construction block 830, which creates newsynthesized packets from the processed samples.

A packet processing scenario may receive, for example, packetscorresponding to M channels, with N signal samples per channel and Rrepetitions of this structure in each packet. After termination of thepacket overhead, packet payloads stored in the packet processor inputbuffers may look as illustrated in FIG. 9, where the payloads includereserved user fields (i.e., fields that are not processes) and signalsamples A₁₁₁, . . . , A_(RMN); B₁₁₁, . . . , B_(RMN); . . . ; X₁₁₁, . .. , X_(RMN). As shown in FIG. 10, each of the samples A₁₁₁, . . . ,A_(RMN), B₁₁₁, . . . , B_(RMN), . . . X₁₁₁, . . . , X_(RMN) may, inturn, include multiple sub-samples, for example, I and Q channelsubsamples I₀, . . . , I_(B-1), Q₀, . . . , Q_(B-1). The sample formatrecognized by each packet processing scenario and/or the operationsperformed in each scenario may be register-configurable.

Beyond bit extension/truncation operations, the sample processing 810may include reordering operations, such as rearranging the order ofsubsamples and/or the order of bits within samples. For example,assuming a sample is 4 bits 1 and 4-bits Q, the sample processing 810may including flipping the I and Q subsamples individually as follows:Input: I₀ I₁ I₂ I₃ Q₀ Q₁ Q₂ Q₃ Output: I₃ I₂ I₁ I₀ Q₃ Q₂ Q₁ Q₀

The sample processing 810 may also rearrange the order of subsamples ina sample as follows: Input: I₀ I₁ I₂ I₃ Q₀ Q₁ Q₂ Q₃ Output: Q₀ Q₁ Q₂ Q₃I₀ I₁ I₂ I₃

The sample processing 810 may also interleave I and Q bits as follows:Input: I₀ I₁ . . . I_(B−1) Q₀ Q₁ . . . Q_(B−1) Output: I₀ Q₀I₁ Q₁ . . .I_(B−1) Q_(B−1)

These and other operations in the sample processing 810 may need to beperformed in a particular order to maintain sample integrity. Forexample, assuming that input samples have an IQ format, are IQinterleaved, and each I and Q subsample has 6 bits, to produce aninterleaved, IQ-flipped, sign-extended output, operations may need to beperformed as follows: Input: I₀ Q₀ I₁ Q₁ I₂ Q₂ I₃ Q₃ I₄ Q₄ I₅ Q₅;Deinterleave I and Q: I₀ I₁ I₂ I₃ I₄ I₅ Q₀ Q₁ Q₂ Q₃ Q₄ Q₅; Sign extendfrom LSB I₀ I₁ I₂ I₃ I₄ I₅ I₅ I₅ Q₀ Q₁ Q₂ Q₃ Q₄ Q₅ Q₅ Q₅; to 8 bits:Flip: I₅ I₅ I₅ I₄ I₃ I₂ I₁ I₀ Q₅ Q₅ Q₅ Q₄ Q₃ Q₂ Q₁ Q₀; Change IQ order:Q₅ Q₅ Q₅ Q₄ Q₃ Q₂ Q₁ Q₀ I₅ I₅ I₅ I₄ I₃ I₂ I₁ I₀; and IQ OutputInterleave: Q₅ I₅ Q₅ I₅ Q₅ I₅ Q₄ I₄ Q₃ I₃ Q₂ I₂ Q₁ I₁ Q₀ I₀.As shown in FIG. 9, after initial processing, samples corresponding torespective ones of the M channels are placed in respective queues.

A given packet processing scenario also may be set up to provide forsumming or other arithmetic operations on payloads from multiplepackets, as illustrated in FIG. 12. In particular, as shown in FIG. 13,a new set of queues 1320 may be established to hold summation resultsfrom summing samples from multiple ports that are stored in other queues1310. If summing is included in a particular scenario, certain bitmanipulation operations of the sample processing, such as deinterleavingand bit extension or deletion, may have to be performed beforesummation, while other operations, such as flipping, I-Q ordering andinterleaving, may need to be performed after summation.

Exemplary use of a packet processing switch chip in a wireless basestation environment according to some embodiments of the presentinvention will now be described with reference to FIGS. 14-20. It willbe appreciated that these examples are offered for purposes ofillustration, and that the present invention is not limited to thespecific operations and architectures illustrated or, more generally, toapplication in wireless applications.

A typical wireless base station architecture is shown in FIG. 14, wherefour RF cards 1410 a, 1410 b, 1410 c, 1410 d provide packets containingradio signal samples to respective input ports 1421 of a packetprocessing switch (PPS) chip 1420. The chip 1420 processes payloads ofthe received packets, producing packets that are transmitted torespective digital signal processors/chip rate processors (DSPs/CRPs)1430 a, 1430 b, 1430 c via respective output ports 1422. It will beappreciated that the DSPs/CRPs 1430 a, 1430 b, 1430 c may, for example,be configured to perform certain baseband processing functions, such asdemodulation and decoding, on the signal samples produced by the RFcards 1410 a, 1410 b, 1410 c, 1410 d. For purposes of the followingexamples shown in FIGS. 15-20, each RF card 1410 a, 1410 b, 1410 c, 1410d has 2 antenna channels, designated as Ant A and Ant B, per card. EachI and Q component is assumed to be 8 bits (1 byte), with no bitinterleaving. The number of adjacent samples in a serial packet from thesame antenna is 2, and the repetition is 2. Each packet from each RFcard will contain 8 samples, including 4 samples from antenna A and 4samples from antenna B. The incoming packets to the PPS chip 1420 on therespective input ports 1421 may look as illustrated in FIG. 15. Somepreprocessing, such as bit extension/deletion operations, will not beillustrated. FIG. 16 illustrates queues 0-7 formed for the respectivechannels after preprocessing.

A first example of packet processing according to some embodiments ofthe present invention is illustrated in FIG. 17. A single packet issynthesized from all of the queues 1-7, with no summing of the samples.The synthesized packet is sent to output ports 20, 22, and 23, addressedto a specific memory address in a target device.

A second example of packet processing according to further embodimentsof the present invention is illustrated in FIG. 18. Multiple synthesizedpackets are generated from the queues 0-7 illustrated in FIG. 16, witheach synthesized packet including 4 samples from each queue. All of thesynthesized packets are sent to output ports 20, 22, and 23, and each isaddressed to a respective memory address of a target device.

In some applications, a user may want to send different packets todifferent destination groups. To do this, the user may send the packetto a group packet processing scenario address using an addressing schemealong the lines described above with reference to FIG. 7. This resultsin parallel operation of multiple packet processing scenarios, with eachinput packet being received by each of the multiple scenarios. Thescenarios can independently process the packets, and generate differentpackets and send them to different ports.

An example of such multiple-packet to multiple-destination packetprocessing according to further embodiments of the present invention isillustrated in FIG. 19. The user sends a packet destined to a grouppacket processing scenario, which maps to two individual packetprocessing scenarios. The first scenario takes inputs from queues 0, 2,4 and 6. The packet produced by the first scenario is sent to outputports 20, 22. The second scenario takes inputs from queues 1, 3, 5, and7. The packet produced by the second scenario is sent to output port 23.

FIG. 20 shows an example wherein summing is enabled. When summing isenabled, respective channels are summed and new queues are formed. Theresulting synthesized packet is sent to output ports 20, 22 and 23.

Referring again to FIG. 1, packets that are received at any of the inputports 110 of a packet processing switch IC chip 100 may be packets(e.g., signal sample packets) that require processing in the packetprocessor 120 or packets that are to be forwarded by the switchingfabric 130 without payload modification. In addition, packets fordifferent packet processing scenarios 132 may be multiplexed at any ofthe input ports. It is generally desired that operations of the packetprocessor 130 be synchronized to maintain desired data rates and to meetother timing criteria. Exemplary operations for synchronizing packetprocessing operations will now be described with reference to FIGS.21-26.

According to some embodiments of the present invention, a packetprocessor operates using a dynamic packet accumulation approach. Onceall incoming packets needed to complete a particular scenario have beenaccumulated at the device, they are processed to form one or more outputpackets associated with the scenario. The output packet(s) is thentransmitted out of the output port(s) associated with the scenario. Insome embodiments, each packet processing scenario processes one inputpacket per port per processing interval, with all input packets beingused by a particular scenario running at substantially the same datarate and having the same size and format.

In some embodiments, dynamic packet accumulation may be implementedusing a state machine that transitions responsive to accumulation andprocessing events. Each scenario may be configured (e.g., viaconfiguration registers, such as the configuration registers 250 in FIG.2) with knowledge of the input ports that will be providing packets.Referring to FIG. 21, after initialization of the state machine (block2105), packets for a scenario begin accumulating (block 2110). In theillustrated embodiments, it is required that all packets destined forthe scenario start accumulating within the accumulation time for a firstarriving packet; the payload for any packet arriving after the firstpacket has completed accumulation is replaced with a default payload(blocks 2115, 2120, 2125). After all packets that meet the requirementto start accumulation in the accumulation window defined by theaccumulation time of the first-arriving packet have completedaccumulation, the packets (i.e., the accumulated packet and, in somecases, any replacement packets) are processed to generate one or moreoutput packets (blocks 2130, 2135), which are then transmitted (block2140). A new accumulation period (block 2110) may commence afterprocessing of the previously received packets begins.

A packet processing scenario may be initialized, for example, by a writeto an initialization register or some other initialization signal. Asucceeding received packet associated with the packet processingscenario (e.g., a packet addressed to the scenario's address) may thenbe considered as the first packet into the scenario.

FIG. 22 illustrates Scenarios 0-4, which can be synchronized independentof one another by sending respective initiation signals Init1-Init4. Ifan initialization signal is sent to a group packet processing scenarioalong the lines described above with reference to FIG. 7, all relatedindividual packet processing scenarios may be initialized. If an inputport is used for more than one scenario, the initialization signals forthe multiple scenarios may be received on the same port or on separateports. After receipt of its initialization signal, a packet processingscenario begins accumulating packets (as shown in the shaded areas),followed by processing of the accumulated packets to synthesize newpackets. As shown in FIG. 22, accumulation of packets for any givenscenario begins with the start of accumulation of a first-arrivingpacket for the scenario. Generally, scenarios do not have to start atthe same time. In further embodiments, a “global” initialization may beachieved, for example, by writing to a global initialization registerand/or by simultaneously providing initialization signals to all packetprocessing scenarios, as shown in FIG. 23. A global initializationsignal may come via any port.

Different scenarios may have different latencies associated with thesize and packet processing needed. Generally, processing time isdependant on the amount of data sent to a scenario (size of packet andnumber of incoming ports), and the type of calculation (samplemanipulation, addition, etc.).

FIG. 24 shows an example in which 5 scenarios 0-4 are in operation.Scenario 0 has space between the arrival of first and second packets onports 0 and 2, illustrating that processing time may dictate how often apacket can be sent to a given scenario from a given port. In particular,processing 2410 for a first iteration of Scenario 0 may occur concurrentwith accumulation of packets for a succeeding second iteration 2420 ofScenario 0. Scenario 2 is similar to Scenario 0, except that Scenario 2has a smaller packet size and a longer processing time, which means thatpackets for Scenario 2 are sent at lower rate than for Scenario 0. Port1 and port 4 receive packets destined for multiple Scenarios 1, 3 and 4,illustrating that a port may be more efficiently used by “hiding” theprocessing time for a particular scenario by sending a packet for adifferent scenario during the processing interval. By multiplexingpackets for multiple scenarios on Port 1 and Port 4, throughput may beincreased.

The dynamic packet accumulation described above can provide significantflexibility in system synchronization. According to some embodiments ofthe present invention, packet processing scenarios wait for the firstpacket to arrive to begin the accumulation phase on a per scenariobasis. This allows for initialization of the packet processor beforebringing up the transmitters connected to the device, because eachscenario begins operating after it begins receiving packets.

If a “standard” packet that is not intended for payload processing(e.g., a packet that is to be routed by a switching fabric, such as theswitching fabric 130 of FIG. 1) is sent to a port that is also receivingpackets that require payload processing, the standard packet may bereceived during idle time (e.g., processing time) of the port. This isillustrated in FIG. 25, where standard packets are multiplexed withpackets intended for packet processing scenarios PPSc1-3. If no portshave sufficient idle time to “fit” a standard packet, then the usercould dedicate ports for packets to be payload-processed and separateports for standard packets.

Accumulation of packets may be limited to an accumulation window definedby arrival of a first packet. This requirement can tie the valid arrivalwindow for packets going to the same scenario to the data rate of thelinks, as illustrated in FIG. 26. As shown, a packet of a group PPSc 0Group 0 on Port 2 arrives first and dictates the valid arrival windowfor all other packets destined for the same scenario PPSc0. As shown, apacket from the same group on Port 5 is late, arriving after the packeton Port 2 has accumulated. The packet on Port 5 may be ignored, e.g., avalue of all zeros (or some other value) may be used in its place duringprocessing. A next accumulation window is started with the arrival of afirst packet of a group PPSc 0 Group 1 after all previous valid Group 0packets have finished processing. As described above, the arrival timeof the next group of packets into the packet processor may be dictatedby the processing time of the previous group.

In further embodiments of the present invention, a time-divisionmultiplexed (TDM) mode of operation may be achieved by sending packetsat times dictated by the longest processing time of all the operativescenarios in the packet processor. Referring to FIG. 27, arrival timesof all packets for packet processing scenarios PPSc 0-3 can becontrolled such that the windows 2710 shown in FIG. 27 are wide enoughto support the longest processing time of all the scenarios. The packetprocessor may be configured to control transmission of outgoing packetsfrom the scenarios PPSc 0-3 to make the device appear to be operating ina TDM mode. In particular, the device may initiate transmission ofoutgoing packets with the start of accumulation of a next incoming groupof packets after processing of the outgoing packets has completed.

FIG. 28 illustrates an alternative configuration for a packet processor2800 (e.g., a packet processor for use in a packet processing switch,such as the packet processing switch 100 of FIG. 1) according to furtherembodiments of the present invention. The packet processor 2800 includesan input packet buffer 2810 configured to store incoming packets. A FIFORead Controller (FRC) 2820 reads data (e.g., signal samples frompayloads of received messages) from the input packet buffer 2810 asspecified by a pointer table 2830. The pointer table 2830 relates inputdata locations in the input packet buffer 2810 to output data locationsin an output packet buffer 2850. A processor 2840 performs samplemanipulation as specified by information stored in packet processingscenario (PPSc) configuration registers 2860. Processed data output bythe processor 2840 is written into the output packet buffer 2850, whichcontructs output packets therefrom.

FIG. 29 illustrates an exemplary configuration for a packet processoralong the lines described above with reference to FIG. 28 according tofurther embodiments of the present invention. A packet processor 2900includes input buffers 2905 that are configured to receive packets froma plurality of ports (not shown). A synchronization monitor module 2910monitors the timing of the incoming packets and extracts headerinformation therefrom via FRCs 2920 that access packets stored in theinput buffers 2905. The extracted header information is provided to apacket framer 2965 for use in constructing output packets includingpayload information generated by processing payload information in theinput packets received by the input buffers 2905.

The FRCs 2920 access packets stored in the input buffers 2905 responsiveto control signals generated by a sample counter and FRC control unit2915. The sample counter and FRC control unit 2915 generates the controlsignals responsive to error and control information generated by thesynchronization monitor module 2910, address information from a pointertable 2950, and packet processing scenario control information fromconfiguration registers of an input/output sample configuration memory2970. The FRCs 2920 transfer payload data from the input buffers 2905 toa set of first bit manipulators 2925, which perform de-interleaving,sign extension and/or bit deletion operations as specified by packetprocessing scenario control information stored in the input/outputsample configuration memory 2970.

A data mux and summing unit 2930 performs summation operations asspecified by packet processing scenario control information stored inthe input/output sample configuration memory 2970, and may furtherperform dynamic/saturation ranging of the summation outputs. The outputof the data mux and summing unit 2930 is provided to a bit manipulator2935, which performs flipping (e.g., MSB/LSB), IQ ordering and/or IQinterleaving operations as specified by packet processing scenariocontrol information stored in the input/output sample configurationmemory 2970. The bit manipulator 2935 provides the processed data, alongwith an address and mask, to an output packet memory 2940. Data istransferred from the output packet memory 2940 to the packet framer2965, which constructs new packets using header information from thesample counter and FRC control unit 2915 and an output packetdestination memory 2960.

It will be appreciated that the packet processing switch architecturesdescribe above are illustrative examples, and that other packetprocessing switch architectures fall within the scope of the presentinvention. More generally, in the drawings and specification, there havebeen disclosed exemplary embodiments of the invention. Although specificterms are employed, they are used in a generic and descriptive senseonly and not for purposes of limitation, the scope of the inventionbeing defined by the following claims.

1. A packet processing integrated circuit chip, comprising: a pluralityof input ports configured to receive packets from respective externalsources; a plurality of output ports configured to transmit packets torespective external recipients; and a packet processor configured toprocess the received packets to generate new packets with new payloadsaccording to selected ones of a plurality of packet processing scenariosbased on destination addresses in the received packets.
 2. A chipaccording to claim 1, wherein the plurality of packet processingscenarios comprises individual packet processing scenarios and grouppacket processing scenarios that invoke parallel processing of a packetby selected ones of the individual packet processing scenarios.
 3. Achip according to claim 1, wherein the packet processor is configurableto extract data from payloads of the received packets and to process theextracted data to produce the new packets with payloads having formatscompatible with data structures of the external recipients.
 4. A chipaccording to claim 1, wherein the packet processor is configurable toperform bit extension, bit truncation, bit reordering and/or bitarithmetic operations on the received packets.
 5. A chip according toclaim 1, wherein timing of each packet processing scenario is controlledresponsive to received packet accumulation for the packet processingscenario.
 6. A chip according to claim 5, wherein the packet processoris configured to initiate packet accumulation for a packet processingscenario responsive to an initialization signal.
 7. A chip according toclaim 1, wherein the packet processing scenarios are user-configurable.8. A chip according to claim 1, wherein the packet processor, the inputports and/or the output ports are configurable via at least one of theinput ports.
 9. A chip according to claim 1, further comprising aninter-integrated circuit (I²C) bus interface, and wherein the packetprocessor, the input ports and/or the output ports are configurable viathe I²C bus interface.
 10. A chip according to claim 1, wherein thereceived packets and the new packets are RapidIO™ (RIO)-compliantpackets.
 11. A chip according to claim 1, further comprising a packetswitching fabric configured to route selected packets from the inputports to selected ones of the output ports without payload modification.12. An interface circuit for conveying data between a first plurality ofcircuit cards and a second plurality of circuit cards, the interfacecircuit comprising: a plurality of input ports configured to receivepackets from respective ones of the first plurality of circuit cards; aplurality of output ports configured to transmit packets to respectiveones of the second plurality of circuit cards; and a packet processorconfigured to process the received packets to generate new packets withnew payloads according to selected ones of a plurality of packetprocessing scenarios based on destination addresses in the receivedpackets.
 13. An interface circuit according to claim 12, wherein theplurality of packet processing scenarios comprises individual packetprocessing scenarios and group packet processing scenarios that invokeparallel processing of a packet by selected ones of the individualpacket processing scenarios.
 14. An interface circuit according to claim12, wherein the packet processor is configurable to extract data frompayloads of the received packets and to process the extracted data toproduce the new packets with payloads having formats compatible withdata structures of processors on the second plurality of circuit cards.15. An interface circuit according to claim 12, wherein the packetprocessor is configurable to perform bit extension, bit truncation, bitreordering and/or bit arithmetic operations on the received packets. 16.An interface circuit according to claim 12, wherein timing of eachpacket processing scenario is controlled responsive to received packetaccumulation for the packet processing scenario.
 17. An interfacecircuit according to claim 12, wherein the packet processing scenariosare user-configurable.
 18. An interface circuit according to claim 12,further comprising a packet switching fabric configured to routeselected packets from the input ports to selected ones of the outputports without payload modification.
 19. An interface circuit accordingto claim 12: wherein the plurality of input ports are configured toreceive packets from respective ones of a plurality of RF cards; andwherein the plurality of output ports are configured to transmit packetsto respective ones of a plurality of baseband cards.